This invention relates to methods and apparatus for detecting defects in a semiconductor test structure to thereby predict product yield.
As feature sizes shrink in the deep sub-micron region, more and more yield losses are ascribed to complex interactions between design and manufacturing, and not just random defects. Typical of such interactions are those where mask patterns do not faithfully reproduce themselves on the wafer and thereby make the chip prone to electrical defects. Such defects are generally classified as systemic defects.
Identifying the location of systematic failures in poorly yielding designs is very difficult. Most test structures routinely tested on silicon are designed to monitor the stability of processes in the fabrication facility and focus mainly on random defects. Localization of systematic defects is currently done by testing of many internal critical blocks in a chip by electrical measurements made at the probe pads. It is sometimes possible to make intelligent guesses to the possible cause of the failure by testing the internal blocks with different test pattern sequences. However, finding the design locations where the unique nature of the layout made it prone to poor reproduction during lithography is still not possible.
Accordingly, there is a need for improved mechanisms for more accurately predicting yield, especially systematic yield, across product chips.